This paper presents an in-memory computing (IMC) architecture developed on an 8x8 array of 8T SRAM cells. This architecture enables both multi-bit parallel Multiply-Accumulate (MAC) operations and standard memory processing through charge-sharing on dedicated read bit-lines. By leveraging the maturity of SRAM technology, this work introduces an 8T SRAM-based IMC architecture that decouples read and write paths, thereby overcoming the reliability limitations of prior 6T SRAM designs. A novel analog-to-digital decoding scheme converts the MAC voltage output into digital counts, which are subsequently interpreted to realize fundamental logic functions including AND/NAND, NOR/OR, XOR/XNOR, and 1-bit addition within the same array. Simulated in a 90 nm CMOS process at 1.8 V supply voltage, the proposed design achieves 8-bit MAC and logical operations at a frequency of 142.85 MHz, with a latency of 0.7 ns and energy consumption of 56.56 fJ/bit per MAC operation and throughput of 15.8 M operations/s.

翻译：本文提出了一种基于8×8阵列8T SRAM单元的存内计算架构。该架构通过专用读取位线上的电荷共享，实现了多比特并行乘累加运算与标准存储器处理。借助SRAM技术的成熟性，本工作提出的8T SRAM存内计算架构将读写路径解耦，从而克服了先前6T SRAM设计的可靠性局限。一种新颖的模数解码方案将MAC电压输出转换为数字计数值，随后通过解析实现包括与/与非、或非/或、异或/同或及1比特加法在内的基本逻辑功能，且所有操作均在同一个阵列内完成。在1.8V电源电压的90纳米CMOS工艺下仿真表明，该设计能以142.85MHz频率执行8比特MAC及逻辑运算，每次MAC操作延迟为0.7纳秒、能耗为56.56飞焦/比特，吞吐量达1580万次操作/秒。