This paper introduces a computer architecture, where part of the instruction set architecture (ISA) is implemented on small highly-integrated field-programmable gate arrays (FPGAs). Small FPGAs inside a general-purpose processor (CPU) can be used effectively to implement custom or standardised instructions. Our proposed architecture directly address related challenges for high-end CPUs, where such highly-integrated FPGAs would have the highest impact, such as on main memory bandwidth. This also enables software-transparent context-switching. The simulation-based evaluation of a dynamically reconfigurable core shows promising results approaching the performance of an equivalent core with all enabled instructions. Finally, the feasibility of adopting the proposed architecture in today's CPUs is studied through the prototyping of fast-reconfigurable FPGAs and studying the miss behaviour of opcodes.

翻译：本文介绍一个计算机结构,在其中部分指令集架构(ISA)是用高集成的小型外地可编程门阵列(FPGAs)执行的。在一般用途处理器(CPU)内,小的FPGAs可以有效地用于执行定制或标准化的指示。我们提议的架构直接解决高端CPU的相关挑战,在这些方面,这种高度集成的FPGAs将产生最大的影响,例如主要记忆带宽。这也能够使软件透明的背景转换。对动态可调整核心的模拟评价显示,在使用所有启用的指令的情况下,等效核心的性能将有望实现。最后,通过快速配置FPGAs(快速配置的FGAs)的原型和对读码的错误行为进行研究,研究在今天的CPU中采用拟议架构的可行性。