An Application-Specific Instruction Set Processor(ASIP) is a specialized microprocessor that provides a trade-off between the programmability of a General Purpose Processor (GPP) and the performance and energy-efficiency of dedicated hardware accelerators. ASIPs are often derived from off-the-shelf GPPs extended by custom instructions tailored towards a specific software workload. One of the most important challenges of designing an ASIP is to find said custom instructions that help to increase performance without being too costly in terms of area and power consumption. To date, solving this challenge is relatively labor-intensive and typically performed manually. Addressing the lack of automation, we present Custom Instruction Designer for RISC-V Extensions (CIDRE), a front-to-back tool for ASIP design. CIDRE automatically analyzes hotspots in RISC-V applications and generates custom instruction suggestions with a corresponding nML description. The nML description can be used with other electronic design automation tools to accurately assess the cost and benefits of the found suggestions. In a RISC-V benchmark study, we were able to accelerate embedded benchmarks from Embench and MiBench by up to 2.47x with less than 24% area increase. The entire process was conducted completely automatically.

翻译：专用指令集处理器（ASIP）是一种专用微处理器，它在通用处理器（GPP）的可编程性与专用硬件加速器的性能和能效之间提供了折衷方案。ASIP通常衍生自现成的GPP，并通过针对特定软件工作负载定制的指令进行扩展。设计ASIP最重要的挑战之一是找到能够提升性能、同时在面积和功耗方面成本不过高的定制指令。迄今为止，解决这一挑战相对劳动密集，通常需要手动完成。针对自动化不足的问题，我们提出了RISC-V扩展定制指令设计器（CIDRE），这是一种面向ASIP设计的前端到后端工具。CIDRE自动分析RISC-V应用程序中的热点，并生成带有相应nML描述的定制指令建议。该nML描述可与其他电子设计自动化工具结合使用，以准确评估所发现建议的成本与收益。在一项RISC-V基准测试研究中，我们成功将来自Embench和MiBench的嵌入式基准测试加速最高达2.47倍，而面积增加不到24%。整个过程完全自动执行。