Automatic code generation is a standard method in software engineering since it improves the code consistency and reduces the overall development time. In this context, this paper presents a design flow for automatic VHDL code generation of mppSoC (massively parallel processing System-on-Chip) configuration. Indeed, depending on the application requirements, a framework of Netbeans Platform Software Tool named MppSoCGEN was developed in order to accelerate the design process of complex mppSoC. Starting from an architecture parameters design, VHDL code will be automatically generated using parsing method. Configuration rules are proposed to have a correct and valid VHDL syntax configuration. Finally, an automatic generation of Processor Elements and network topologies models of mppSoC architecture will be done for Stratix II device family. Our framework improves its flexibility on Netbeans 5.5 version and centrino duo Core 2GHz with 22 Kbytes and 3 seconds average runtime. Experimental results for reduction algorithm validate our MppSoCGEN design flow and demonstrate the efficiency of generated architectures.

翻译：自动代码生成是软件工程的一个标准方法,因为它改善了代码的一致性并缩短了总体开发时间。 在这方面,本文件展示了自动生成 mHDL 代码的 mppSoC (大规模平行处理系统在芯片上)配置的设计流程。 事实上,根据应用要求,开发了一个名为 MppSoCGEN 的Netbeans平台软件工具框架,以加快复杂 mppSoC 的设计过程。 从结构参数设计开始, VHDL 代码将自动使用解析方法生成。 提议配置规则要有一个正确有效的 VHDL 语法配置。 最后, 将为 Stratix II 设备家族自动生成 mppSoC 结构的处理器元素和网络型号模型。 我们的框架提高了Netbeans 5. 5 版本和 centrino duo Core 2GHz 的灵活性, 平均运行时间为 22 Kbytes 和 3 秒。 削减算法的实验结果验证了我们的 MppSoCGEN 设计流程并演示了生成结构的效率 。