As quantum computing technology matures, industry is adopting modular quantum architectures to keep quantum scaling on the projected path and meet performance targets. However, the complexity of chiplet-based quantum devices, coupled with their growing size, presents an imminent scalability challenge for quantum compilation. Contemporary compilation methods are not well-suited to chiplet architectures - in particular, existing qubit allocation methods are often unable to contend with inter-chiplet links, which don't necessarily support a universal basis gate set. Furthermore, existing methods of logical-to-physical qubit placement, swap insertion (routing), unitary synthesis, and/or optimization, are typically not designed for qubit links of significantly varying latency or fidelity. In this work, we propose SEQC, a hierarchical parallelized compilation pipeline optimized for chiplet-based quantum systems, including several novel methods for qubit placement, qubit routing, and circuit optimization. SEQC attains a $9.3\%$ average increase in circuit fidelity (up to $49.99\%$). Additionally, owing to its ability to parallelize compilation, SEQC achieves $3.27\times$ faster compilation on average (up to $6.74\times$) over a chiplet-unaware Qiskit baseline.

翻译：随着量子计算技术的成熟，工业界正采用模块化量子架构以维持量子扩展按预期路径发展并满足性能目标。然而，基于芯片粒的量子设备复杂性与其日益增大的规模相结合，对量子编译提出了迫在眉睫的可扩展性挑战。现有编译方法并不完全适用于芯片粒架构——特别是现有的量子比特分配方法通常难以应对芯片粒间链路，这些链路不一定支持通用基础门集。此外，现有的逻辑-物理量子比特布局、交换插入（路由）、酉合成和/或优化方法通常未针对具有显著不同延迟或保真度的量子比特链路进行设计。在本工作中，我们提出了SEQC，一种针对基于芯片粒的量子系统优化的分层并行化编译流水线，包括多种新颖的量子比特布局、量子比特路由和电路优化方法。SEQC实现了电路保真度平均提升9.3%（最高达49.99%）。此外，得益于其并行化编译能力，SEQC相比未考虑芯片粒架构的Qiskit基准方法，平均编译速度提升3.27倍（最高达6.74倍）。