We introduce an approach to designing FPGA-accelerated middleboxes that simplifies development, debugging, and performance tuning by decoupling the tasks of hardware-accelerator implementation and software-application programming. Rosebud is a framework that links hardware accelerators to a high-performance packet processing pipeline through a standardized hardware/software interface. This separation of concerns allows hardware developers to focus on optimizing custom accelerators while freeing software programmers to reuse, configure, and debug accelerators in a fashion akin to software libraries. We show the benefits of the Rosebud framework by building a firewall based on a large blacklist and porting the Pigasus IDS pattern-matching accelerator in less than a month. Our experiments demonstrate that Rosebud delivers high performance, serving ~200 Gbps of traffic while adding only 0.7-7 microseconds of latency.

翻译：我们提出了一种设计 FPGA 加速器中间盒的方法，该方法通过将硬件加速器的实现和软件应用程序编程的任务分离，简化了开发、调试和性能调优。Rosebud 是一个框架，通过标准化的硬件/软件接口将硬件加速器链接到高性能数据包处理管道。这种关注点的分离使硬件开发人员可以专注于优化定制加速器，同时允许软件程序员像使用软件库一样重用、配置和调试加速器。我们通过构建一个基于大型黑名单的防火墙，并在不到一个月的时间内移植了Pigasus IDS模式匹配加速器，展示了 Rosebud 框架的优势。我们的实验证明，Rosebud 可以在仅增加 0.7-7 微秒的延迟的同时服务于 ~200 Gbps 的流量。