The scaling of advanced packaging technologies provides abundant interconnection resources for 2.5D/3D heterogeneous integration (HI), thereby enabling the construction of larger-scale VLSI systems with higher energy efficiency in data movement. However, conventional input/output (I/O) circuitry, including electrostatic discharge (ESD) protection and signaling, introduces significant area overhead. Prior studies have identified this overhead as a major constraint in reducing chiplet size below 100 mm2. In this study, we revisit reliability requirements from the perspective of chiplet interface design. Through parasitic extraction and simulation program with integrated circuit emphasis (SPICE) simulations, we demonstrate that ESD protection and inter-chiplet signaling can be substantially simplified in future 2.5D/3D packaging technologies. Such simplification, in turn, paves the road for further chiplet miniaturization and improves the composability and reusability of tiny chiplets.

翻译：先进封装技术的尺度缩减为2.5D/3D异构集成提供了丰富的互连资源，从而能够构建具有更高数据移动能效的大规模超大规模集成电路系统。然而，传统的输入/输出电路，包括静电放电保护和信号传输，引入了显著的面积开销。先前研究已确认该开销是制约芯粒尺寸缩减至100平方毫米以下的主要因素。本研究从芯粒接口设计的角度重新审视可靠性要求。通过寄生参数提取和集成电路重点仿真程序的模拟，我们证明在未来2.5D/3D封装技术中，静电放电保护和芯粒间信号传输可得到大幅简化。这种简化为进一步实现芯粒微型化铺平了道路，并提升了微型芯粒的可组合性与可复用性。