The scan-based testing has been widely used as a Design-for-Test (DfT) mechanism for most recent designs. It has gained importance not only in manufacturing testing but also in online testing and debugging. However, the multiplexer-based scan flip-flop, which is the basic building block of scan chain, is troubled with a set of issues such as mux-induced additional delay and test power among others. The effect of additional delay due to the multiplexer on the functional path (D in path) has started influencing the clock period, particularly at the lower technology nodes for the high-performance design. In this work, we propose two scan flip-flop designs using 10nm FinFET technology to address the problem of mux-induced delay and internal power. The proposed designs have been experimentally validated for performance gain and power reduction and compared to the existing designs.

翻译：基于扫描的测试已被广泛用作最近设计的设计测试(DfT)机制,不仅在制造测试中,而且在在线测试和调试中都越来越重要,然而,作为扫描链基本构件的多轴扫描翻转螺旋杆,遇到了一系列问题,如混凝土引发的额外延迟和测试能力等。多轴在功能路径(路径中的D)上的功能路段(路径中的D)造成的额外延迟效应已开始影响时钟周期,特别是在高性能设计技术节点较低的时钟周期。在这项工作中,我们提议用10nm FinFET技术扫描两部翻转螺旋形设计,以解决混凝土引发的延迟和内部动力问题。提议的设计已经经过实验验证,以获得性能和功率,并与现有设计进行比较。