The memory wall bottleneck is a key challenge across many data-intensive applications. Multi-level FeFET-based embedded non-volatile memories are a promising solution for denser and more energy-efficient on-chip memory. However, reliable multi-level cell storage requires careful optimizations to minimize the design overhead costs. In this work, we investigate the interplay between FeFET device characteristics, programming schemes, and memory array architecture, and explore different design choices to optimize performance, energy, area, and accuracy metrics for critical data-intensive workloads. From our cross-stack design exploration, we find that we can store DNN weights and social network graphs at a density of over 8MB/mm^2 and sub-2ns read access latency without loss in application accuracy.

翻译：记忆墙瓶颈是许多数据密集型应用中的一个关键挑战。 多级的基于FeFET的内嵌非挥发性记忆对于更稠密、更节能的芯片内存来说是一个很有希望的解决方案。 但是,可靠的多级细胞储存需要谨慎优化,以尽量减少设计间接费用。 在这项工作中,我们调查FeFET设备特性、编程计划和记忆阵列结构之间的相互作用,并探索不同的设计选择,以优化关键数据密集型工作量的性能、能源、面积和准确度度量度。 从我们跨堆设计探索中,我们发现我们可以将DNN重量和社会网络图存储在8MB/mm ⁇ 2和次二人读取时间的密度,而不会丧失应用精确度。