The design of efficient hardware accelerators for high-throughput data-processing applications, e.g., deep neural networks, is a challenging task in computer architecture design. In this regard, High-Level Synthesis (HLS) emerges as a solution for fast prototyping application-specific hardware starting from a behavioural description of the application computational flow. This Design-Space Exploration (DSE) aims at identifying Pareto optimal synthesis configurations whose exhaustive search is often unfeasible due to the design-space dimensionality and the prohibitive computational cost of the synthesis process. Within this framework, we effectively and efficiently address the design problem by proposing, for the first time in the literature, graph neural networks that jointly predict acceleration performance and hardware costs of a synthesized behavioral specification given optimization directives. The learned model can be used to rapidly approach the Pareto curve by guiding the DSE, taking into account performance and cost estimates. The proposed method outperforms traditional HLS-driven DSE approaches, by accounting for arbitrary length of computer programs and the invariant properties of the input. We propose a novel hybrid control and data flow graph representation that enables training the graph neural network on specifications of different hardware accelerators; the methodology naturally transfers to unseen data-processing applications too. Moreover, we show that our approach achieves prediction accuracy comparable with that of commonly used simulators without having access to analytical models of the HLS compiler and the target FPGA, while being orders of magnitude faster. Finally, the learned representation can be exploited for DSE in unexplored configuration spaces by fine-tuning on a small number of samples from the new target domain.

翻译：为高通量数据处理应用设计高效硬件加速器,例如深神经网络,是计算机结构设计中的一项艰巨任务。在这方面,高级合成(HLS)是从对应用计算流程的行为描述出发,作为快速原型应用特定硬件的解决方案,从对应用计算流程进行行为描述开始的。设计-空间探索(DSE)的目的是查明由于设计-空间空间的高度和合成过程的计算成本过高而往往无法进行彻底搜索的Pareto最佳合成配置。在此框架内,我们切实有效地解决设计问题,首先在文献中提议,通过图形神经网络,共同预测加速性业绩和综合行为规格的硬件成本。学习模型可用于通过指导DSE(DSE)快速接近Pareto曲线,同时考虑到性能和成本估算。拟议方法将传统的HLSS-驱动DSE(DSE)方法与传统的计算机程序任意长度和投入的不稳定性计算结果相违背。我们提议,在文献中采用新的混合节能配置和可比较性数据网络的精确性数据网络(Sureal-LS)模型,最终显示我们使用的硬性数据转换方法,从而能够对硬性数据进行再编算。