We present the first single-input multiple-output (SIMO) receiver ASIC that jointly performs jammer mitigation, channel estimation, and data detection. The ASIC implements a recent algorithm called siMultaneous mitigAtion, Estimation, and Detection (MAED). MAED mitigates smart jammers via spatial filtering using a nonlinear optimization problem that unifies jammer estimation and nulling, channel estimation, and data detection to achieve state-of-the-art error-rate performance under jamming. The design supports eight receive antennas and enables mitigation of smart jammers as well as of barrage jammers. The ASIC is fabricated in 22 nm FD-SOI, has a core area of 0.32 mm$^2$, and achieves a throughput of 100 Mb/s at 223 mW, thus delivering 3$\times$ higher per-user throughput and 4.5$\times$ higher area efficiency than the state-of-the-art jammer-resilient detector.

翻译：我们首次提出了一款单输入多输出（SIMO）接收器专用集成电路（ASIC），该芯片能够联合执行干扰抑制、信道估计与数据检测。该ASIC实现了一种名为“同时缓解、估计与检测”（MAED）的最新算法。MAED通过非线性优化问题实现空间滤波，将干扰估计与抑制、信道估计以及数据检测统一起来，从而在干扰环境下实现最先进的误码率性能。该设计支持八根接收天线，能够有效抑制智能干扰与阻塞式干扰。该ASIC采用22纳米FD-SOI工艺制造，核心面积为0.32 mm²，在223 mW功耗下实现100 Mb/s的吞吐量，相比现有最先进的抗干扰检测器，其单用户吞吐量提升3倍，面积效率提升4.5倍。