Vision Transformers (ViTs) have established new performance benchmarks in vision tasks such as image recognition and object detection. However, these advancements come with significant demands for memory and computational resources, presenting challenges for hardware deployment. Heterogeneous compute-in-memory (CIM) accelerators have emerged as a promising solution for enabling energy-efficient deployment of ViTs. Despite this potential, monolithic CIM-based designs face scalability issues due to the size limitations of a single chip. To address this challenge, emerging chiplet-based techniques offer a more scalable alternative. However, chiplet designs come with their own costs, as they introduce expensive communication, which can hinder improvements in throughput. This work introduces Hemlet, a heterogeneous CIM chiplet system designed to accelerate ViT workloads. Hemlet enables flexible resource scaling through the integration of heterogeneous analog CIM (ACIM), digital CIM (DCIM), and Intermediate Data Process (IDP) chiplets. To improve throughput while reducing communication overhead, it employs a group-level parallelism (GLP) mapping strategy and system-level dataflow optimization, achieving speedups ranging from 1.89x to 4.47x across various hardware configurations within the chiplet system. Our evaluation results show that Hemlet can reach a throughput of 9.24 TOPS with an energy efficiency of 4.98 TOPS/W.

翻译：视觉Transformer（ViT）已在图像识别与目标检测等视觉任务中确立了新的性能基准。然而，这些进展伴随着对内存与计算资源的显著需求，为硬件部署带来了挑战。异构存内计算（CIM）加速器已成为实现ViT能效部署的有前景解决方案。尽管具备潜力，基于单片CIM的设计受限于单芯片尺寸而面临可扩展性问题。为应对这一挑战，新兴的小芯片技术提供了更具可扩展性的替代方案。但小芯片设计亦存在成本问题，其引入的高昂通信开销可能阻碍吞吐量提升。本研究提出Hemlet——一种专为加速ViT工作负载设计的异构CIM小芯片系统。Hemlet通过集成异构模拟存内计算（ACIM）、数字存内计算（DCIM）及中间数据处理（IDP）小芯片，实现了灵活的资源扩展。为在降低通信开销的同时提升吞吐量，该系统采用组级并行（GLP）映射策略与系统级数据流优化，在小芯片系统内不同硬件配置下实现了1.89倍至4.47倍的加速比。评估结果表明，Hemlet可实现9.24 TOPS的吞吐量，能效达4.98 TOPS/W。