Recent advancements in Artificial Intelligence (AI) algorithms have sparked a race to enhance hardware capabilities for accelerated task processing. While significant strides have been made, particularly in areas like computer vision, the progress of AI algorithms appears to have outpaced hardware development, as specialized hardware struggles to keep up with the ever-expanding algorithmic landscape. To address this gap, we propose a new accelerator architecture, called messaging-based intelligent processing unit (m-IPU), capable of runtime configuration to cater to various AI tasks. Central to this hardware is a programmable interconnection mechanism, relying on message passing between compute elements termed Sites. While the messaging between compute elements is a known concept for Network-on-Chip or multi-core architectures, our hardware can be categorized as a new class of coarse-grained reconfigurable architecture (CGRA), specially optimized for AI workloads. In this paper, we highlight m-IPU's fundamental advantages for machine learning applications. We illustrate the efficacy through implementations of a neural network, matrix multiplications, and convolution operations, showcasing lower latency compared to the state-of-the-art. Our simulation-based experiments, conducted on the TSMC 28nm technology node, reveal minimal power consumption of 44.5 mW with 94,200 cells utilization. For 3D convolution operations on (32 x 128) images, each (256 x 256), using a (3 x 3) filter and 4,096 Sites at a frequency of 100 MHz, m-IPU achieves processing in just 503.3 milliseconds. These results underscore the potential of m-IPU as a unified, scalable, and high-performance hardware architecture tailored for future AI applications.

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