This work introduces the Re$^{\text{2}}$MaP method, which generates expert-quality macro placements through recursively prototyping and packing tree-based relocating. We first perform multi-level macro grouping and PPA-aware cell clustering to produce a unified connection matrix that captures both wirelength and dataflow among macros and clusters. Next, we use DREAMPlace to build a mixed-size placement prototype and obtain reference positions for each macro and cluster. Based on this prototype, we introduce ABPlace, an angle-based analytical method that optimizes macro positions on an ellipse to distribute macros uniformly near chip periphery, while optimizing wirelength and dataflow. A packing tree-based relocating procedure is then designed to jointly adjust the locations of macro groups and the macros within each group, by optimizing an expertise-inspired cost function that captures various design constraints through evolutionary search. Re$^{\text{2}}$MaP repeats the above process: Only a subset of macro groups are positioned in each iteration, and the remaining macros are deferred to the next iteration to improve the prototype's accuracy. Using a well-established backend flow with sufficient timing optimizations, Re$^{\text{2}}$MaP achieves up to 22.22% (average 10.26%) improvement in worst negative slack (WNS) and up to 97.91% (average 33.97%) improvement in total negative slack (TNS) compared to the state-of-the-art academic placer Hier-RTLMP. It also ranks higher on WNS, TNS, power, design rule check (DRC) violations, and runtime than the conference version ReMaP, across seven tested cases. Our code is available at https://github.com/lamda-bbo/Re2MaP.

翻译：本文提出Re$^{\\text{2}}$MaP方法，通过递归原型构建与树形重定位打包生成专家级质量的宏单元布局。我们首先执行多层次宏单元分组与功耗-性能-面积（PPA）感知的单元聚类，生成统一的连接矩阵以捕获宏单元与簇之间的线长及数据流关系。随后，利用DREAMPlace构建混合尺寸布局原型，获取每个宏单元与簇的参考位置。基于此原型，我们提出ABPlace——一种基于角度的解析方法，通过在椭圆上优化宏单元位置，使宏单元均匀分布在芯片外围区域，同时优化线长与数据流。接着设计基于打包树的宏单元重定位流程，通过进化搜索优化融合专家经验启发式代价函数（该函数涵盖多种设计约束），联合调整宏单元组及其内部宏单元的位置。Re$^{\\text{2}}$MaP迭代执行上述过程：每次迭代仅定位部分宏单元组，剩余宏单元递延至后续迭代以提升原型精度。采用具备充分时序优化的成熟后端流程进行验证，与当前最先进的学术布局工具Hier-RTLMP相比，Re$^{\\text{2}}$MaP在最差负时序裕量（WNS）上最高提升22.22%（平均10.26%），在总负时序裕量（TNS）上最高提升97.91%（平均33.97%）。在七个测试案例中，其在WNS、TNS、功耗、设计规则检查（DRC）违例数量及运行时间等指标上均优于会议版本ReMaP。代码已开源：https://github.com/lamda-bbo/Re2MaP。