Static Random-Access Memory (SRAM) yield analysis is essential for semiconductor innovation, yet research progress faces a critical challenge: the large gap between simplified academic models and the complexities observed in practice. The lack of open, higher-fidelity benchmarks has hindered reproducibility and transferability, as promising academic techniques often fail to carry over to more realistic settings. We present OpenYield, an open-source ecosystem that aims to narrow this gap through three contributions: (i) An SRAM circuit generator that explicitly incorporates second-order effects (interconnect/line parasitics, inter-cell leakage coupling, and peripheral-circuit variations) that are commonly omitted in academic studies. (ii) A standardized evaluation platform with a simple interface and baseline yield-analysis implementations to enable fair comparisons and reproducible research on these higher-fidelity circuits. (iii) An optimization platform for transistor-level sizing under these models, supporting reproducible studies of robustness/efficiency trade-offs. OpenYield aims to foster more reproducible and transferable progress in SRAM-yield research. The framework is publicly available at https://github.com/ShenShan123/OpenYield

翻译：静态随机存取存储器（SRAM）的良率分析对于半导体创新至关重要，然而研究进展面临一个关键挑战：简化的学术模型与实际观察到的复杂性之间存在巨大差距。缺乏开放、高保真度的基准测试阻碍了研究的可复现性和可迁移性，因为许多有前景的学术技术往往无法在更现实的场景中有效应用。我们提出了OpenYield，这是一个开源生态系统，旨在通过以下三个贡献来缩小这一差距：（i）一个SRAM电路生成器，明确纳入了学术研究中常被忽略的二阶效应（互连线寄生效应、单元间泄漏耦合以及外围电路变异）。（ii）一个标准化的评估平台，具有简洁的接口和基线良率分析实现，以支持在这些高保真度电路上进行公平比较和可复现的研究。（iii）一个在这些模型下进行晶体管级尺寸优化的平台，支持对鲁棒性与效率权衡的可复现研究。OpenYield旨在促进SRAM良率研究领域更具可复现性和可迁移性的进展。该框架已在https://github.com/ShenShan123/OpenYield公开提供。