Virtually indexed and virtually tagged (VIVT) caches are an attractive option for micro-processor level-1 caches, because of their fast response time and because they are cheaper to implement than more complex caches such as virtually-indexed physical-tagged (VIPT) caches. The level-1 VIVT cache becomes even simpler to construct if it is implemented as a direct-mapped cache (VIVT-DM cache). However, VIVT and VIVT-DM caches have some drawbacks. When the number of sets in the cache is larger than the smallest page size, there is a possibility of synonyms (two or more virtual addresses mapped to the same physical address) existing in the cache. Further, maintenance of cache coherence across multiple processors requires a physical to virtual translation mechanism in the hardware. We describe a simple, efficient reverse lookup table based approach to address the synonym and the coherence problems in VIVT (both set associative and direct-mapped) caches. In particular, the proposed scheme does not disturb the critical memory access paths in a typical micro-processor, and requires a low overhead for its implementation. We have implemented and validated the scheme in the AJIT 32-bit microprocessor core (an implementation of the SPARC-V8 ISA) and the implementation uses approximately 2% of the gates and 5.3% of the memory bits in the processor core.

翻译：虚拟索引和贴贴( VIVT) 缓存对于微型处理器一级缓存来说是一个有吸引力的选项,因为它们反应时间快,而且执行比更复杂的缓存更便宜,例如几乎索引化的实物标记(VIPT) 缓存。如果将其作为直接测量的缓存(VIVT-DM缓存)加以执行,则一级VIVT 缓存就更简单了。然而, VVT 和VIVT-DM 缓存有一些缺点。当缓存的组数大于最小的页面大小时,就有可能在缓存中出现同义词(两个或两个以上的虚拟地址被绘制到相同的实物地址) 。此外,维护多个处理器之间的缓存一致性需要硬件中的物理到虚拟翻译机制。我们描述一个简单、高效的反向翻转表格方法,以解决同义和VVVT 中的一致性问题(同时设置连线和直接测量) 缓存。特别是,拟议的计划不会在典型的I- 微处理器中扰乱关键的存路径,8 在常规的IM-C 执行过程中,需要一个低的S- Pad- PAR 系统。